The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, to a technique effective when applied to a semiconductor device including a fin-type transistor.
A fin-type transistor is known as a field effect transistor whose: operation speed is high; leakage current and power consumption can be reduced; and miniaturization can be achieved. The fin-type transistor (FINFET: Fin Field Effect Transistor) is a semiconductor element that has, for example, both a semiconductor layer pattern formed over a substrate as a channel layer and a gate electrode formed to stretch over the pattern.
EEPROMs (Electrically Erasable and Programmable Read Only Memory) are widely used as nonvolatile semiconductor memory devices in which data can be electrically written/erased. Each of these memory devices represented by the flash memories now widely used has, under the gate electrode of a MISFET, a conductive floating gate electrode or a trap insulating film, which is surrounded by an oxide film, so that a charge storage state in the floating gate or the trap insulating film, i.e., memory data, is read as the threshold value of a transistor. This trap insulating film refers to an insulating film in which charges can be stored, and examples thereof include a silicon nitride film, and the like. Each of these memory devices is operated as a memory element by shifting the threshold value of a MISFET with charges being injected/discharged into/from such a charge storage region. An example of this flash memory is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2015-5746) discloses that an active base is provided over a substrate and a memory cell is formed over each of a plurality of fins protruding from the upper surface of the active base.
Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2005-276930) discloses that when trenches, into each of which an element isolation region for isolating a plurality of memory cells from each other is to be embedded, are formed, multiple types of trenches, each having an aspect ratio different from those of the others, are formed in order to improve the embeddability of an insulating film into the trench.